1. Field of the Invention
The present invention relates to a method of controlling warpage in dielectrically-isolated (DI) silicon wafers utilizing thick layers of polysilicon and, more particularly, to a method of controlling warpage utilizing a multilayering technique for growing polysilicon which consists of alternating growth rates via periodic fluctuations in a preselected growth parameter. This multilayering growth technique results in stress accommodation by substructural layering and stress reduction by strain-induced recrystallization within the polysilicon layer.
2. Description of the Prior Art
In the manufacture of certain types of semiconductor integrated circuits, it is necessary to prepare dielectrically-isolated (DI) single-crystal silicon substrates or dielectrically-isolated (DI) single-crystal regions (or tubs) within the body of a polycrystalline silicon (polysilicon) matrix. Various circuit elements, such as transistors, diodes, capacitors, resistors, etc. may be formed in the single-crystal silicon regions and interconnected with each other to form a monolithic integrated circuit. The continually increasing widespread use of integrated circuits (ICs) requires improved isolation techniques and characteristics beyond those obtainable with p-n junctions. Additionally, junction isolated planar circuits have several limitations that dielectric isolation can substantially impact. In particular, dielectric isolation allows increased packing density, elimination of unwanted SCR action with the substrate (particularly important in crosspoints and radiation-hardened devices), increased operational speed in the circuit by reduction of stray capacitance, and higher collector-base breakdown voltage.
The traditional dielectric isolation technique involves the deposition of a thick polysilicon layer on the oxidized most side of the wafer. Its purpose is to fill the moats and provide both support and a reference surface with respect to which the single crystal substrate can be thinned. The individual isolated single crystal islands embedded in the polysilicon matrix can then easily be handled during subsequent IC processing. A problem with this traditional isolation technique is that the deposition of a thick polysilicon layer is known to create severe, uncontrollable, wafer warpage which is mainly due to the large internal stress generated during polysilicon growth. In contrast, the internal stresses induced by the mismatch in thermal expansion of the polysilicon layer and the (100) silicon substrate are negligible. Therefore, the major deformation of the DI wafer is a consequence of the growth kinetics of the polysilicon. During high temperature silicon growth, the polysilicon buried behind the advancing interface of the growing layer tries to contract perpendicular to the growth direction via material transport across grain boundaries. This contraction leaves the polysilicon layer in a grown-in tensile state of stress which causes the structure to bow.
One method of reducing the bowing of DI wafers is disclosed in U.S. Pat. No. 3,862,852 issued to T. I. Kamins on Jan. 28, 1975. Kamins discovered that the presence of oxygen in the gas used to deposit the polysilicon resulted in increasing the warpage. Accordingly, Kamins discloses a method of depositing polysilicon in a gaseous environment in which the ratio of oxygen atoms to hydrogen atoms is minimized. For example, he uses an oxygen concentration of less than ten parts per million parts hydrogen when the polysilicon is deposited at 1100.degree. C. at a rate of 4 microns per minute. However, it has been determined that as the deposition temperature or the deposition rate decreases, the amount of oxygen which can be tolerated likewise decreases, resulting in a set of operating conditions which is extremely difficult to control.
Another known method of preparing DI wafers is disclosed in U.S. Pat. No. 4,079,506 issued to T. Suzuki et al on Mar. 21, 1978 and further discussed in an article entitled "Deformation in Dielectric-Isolated Substrates and Its Control by a Multilayer Polysilicon Support Structure" by T. Suzuki et al appearing in the Journal of the Electrochemical Society, Vol. 127, No. 7, July 1980 at pp. 1537-1542. Suzuki et al believes that the deformation of substrates during DI processing occurs during both the polysilicon deposition and subsequent oxidation/diffusion for junction formation. The former kind of deformation is caused by the tensile component of the stress generated through the high temperature contraction of the polysilicon. The latter type of deformation is compressive in nature and is caused by the differential oxidation rate between the top polysilicon layer and the single crystal substrate. In the Suzuki et al technique, a plurality of silicon single-crystal regions are supported by a laminated structure comprising an alternate stacking of oxide films and polycrystalline silicon (polysilicon) layers. A silicon oxide film is interposed between the single-crystal regions or islands and the multiple layer support structure for isolating the regions from one another as well as from the support structure. According to this known method, the formation of three to twelve silicon polycrystalline layers in the support structure can reduce bendings of the substrate resulting from the growth stress of the polycrystalline layers. An improved method of providing this laminated structure is disclosed in U.S. Pat. No. 4,310,965 issued to J. Horiuchi et al on Jan. 19, 1982. The improved technique relates to limiting the thickness of each layer in the interposed structure in associated with the equation x&lt;(y/40), where x is the thickness of each layer (in microns) and y is the ultimate thickness of the substrate.
Although these above-described known techniques appear to solve the bending or warpage problem, the use of such an alternate multiple layer structure results in a delicate, time consuming, as well as expensive, method for manufacturing isolated single-crystal regions. Moreover, the deposition of the polyorystalline layers takes place at high temperatures capable of deleteriously effecting the characteristics of the silicon single crystal tub regions.